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Six-String White LED Driver with Active
Current Balancing for LCD Panel Applications
Pin Description (continued)
PIN
11
12
13
14
15
16
17
18
19
20
EP
NAME
FB6
CS
EXT
OV
V CC
IN
CCV
ISET
FSET
CPLL
EP
FUNCTION
LED String 6 Cathode Connection. FB6 is the open-drain output of an internal regulator, which controls
current through FB6. FB6 can sink up to 25mA. If unused, connect FB6 to GND.
Step-Up Controller Current-Sense Input. Connect the CS input to a ground-referenced sense resistor to
measure the current in the external MOSFET switch.
External MOSFET Gate-Drive Output
Overvoltage Sense. Connect OV to the center tap of a resistive voltage-divider from V OUT to ground. The
detection threshold for voltage limiting at OV is 1.23V (typ).
5V Linear Regulator Output. V CC provides power to the MAX8790 and is also used to bias the gate driver
for the external MOSFET. Bypass V CC to GND with a ceramic capacitor of 1μF or greater. If V IN is less
than or equal to 5.5V, connect V CC to IN to the disable the internal LDO and use the external 5V supply to
V CC . When SHDN is low, the internal linear regulator is disabled.
Supply Input. V IN biases the internal 5V linear regulator that powers the device. Bypass IN to GND directly
at the pin with a 0.1μF or greater ceramic capacitor.
Step-Up Converter Compensation Pin. Connect a 0.1μF ceramic capacitor and 1.2k Ω resistor from CCV to
GND. When the MAX8790 shuts down, CCV is discharged to 0V through an internal 20k Ω resistor.
Full-Scale LED Current Adjustment Pin. The resistance from ISET to GND controls the full-scale current in
each LED string:
I LEDmax = 20mA x 100k Ω /R ISET
The acceptable resistance range is 80k Ω < R ISET < 133k Ω , which corresponds to full-scale LED current of
25mA > I LEDmax > 15mA. Connect ISET to V CC for a default full-scale LED current of 20mA.
PLL Free-Running Frequency Control Pin. The resistance from FSET to GND controls the PLL oscillator’s
free-running frequency, f PLL :
f PLL = 1 / (10 x R FSET x 800pF)
The capture range is 0.6 x f PLL to f PLL . The acceptable resistance range for FSET is 250k Ω < R FSET <
754k Ω , which corresponds to a frequency range of 500Hz > f PLL > 166Hz. The resulting capture
frequency range is 100Hz to 500Hz.
Phase-Locked Loop-Compensation Capacitor Pin. The capacitance at CPLL compensates the PLL loop
response. Connect a 0.1μF ceramic capacitor from CPLL to GND.
Exposed Backside Pad. Solder to the circuit board ground plane with sufficient copper connection to
ensure low thermal resistance. See the PCB Layout Guidelines section.
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9
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